WM8352
Production Data
REFER TO
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
CODEC SYSCLK enable
R11 (0Bh)
Power mgmt
(4)
14
SYSCLK_ENA
0
0 = disabled
1 = enabled
13
8
ADC_HPF_ENA
TOCLK_ENA
DACR_ENA
DACL_ENA
1
0
0
0
0
High Pass Filter enable
0 = disabled
1 = enabled
Slow clock enable. Used the zero cross timeout.
0 = disabled
1 = enabled
5
Right DAC enable
0 = disabled
1 = enabled
4
Left DAC enable
0 = disabled
1 = enabled
3
ADCR_ENA
Right ADC enable
0 = disabled
1 = enabled
When ADCR and ADCL are used together as a
stereo pair, then both ADCs must be enabled
together using a single register write to Register R11
(0Bh).
2
ADCL_ENA
0
Left ADC enable
0 = disabled
1 = enabled
When ADCR and ADCL are used together as a
stereo pair, then both ADCs must be enabled
together using a single register write to Register R11
(0Bh).
Register 0Bh Power mgmt (4)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R12 (0Ch)
Power mgmt
(5)
12
CODEC_ENA
0
Master codec enable bit. Until this bit is set, all codec
registers are held in reset.
0 = All codec registers held in reset
1 = Codec registers operate normally.
Reset by state machine.
11
10
9
RTC_TICK_ENA
OSC32K_ENA
CHG_ENA
1
1
1
Real Time Clock control.
0 = RTC is disabled
1 = RTC is enabled.
Protected by security key. Reset by state machine.
Default held in metal mask.
32kHz crystal oscillator control
0 = 32kHz OSC is disabled
1 = 32kHz OSC is enabled
Protected by security key. Reset by state machine.
Default held in metal mask.
Charger control
CHG_ENA bit selects battery charger current control
0 = Set battery charger current to zero
1 = Enable battery charge control
Protected by security key. Reset by state machine.
Default held in metal mask.
8
SW_VRTC_ENA
0
SW_VRTC control
PD, February 2011, Rev 4.4
226
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
