Production Data
WM8195
PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8195. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal
may not be readily available. The programmable VSMP detect circuit in the WM8195 allows the
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register
clock, when applied to the VSMP pin.
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.
This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.
Figure 19 shows the internal VSMP pulses that can be generated by this circuit for a typical clock
input signal. The internal VSMP pulse is then applied to the timing control block in place of the
normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising
MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
MCLK
INPUT
PINS
VSMP
POSNNEG = 1
VS
VS
VS
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
POSNNEG = 0
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
Figure 19 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS.
PD Rev 4.1 July 2005
21
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
