WM8195
Production Data
POWER SUPPLY
The WM8195 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)
supplies.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit and SELPD bit low. Alternatively, when control bit SELPD is
high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the
user to optimise power dissipation in certain modes, or to define an intermediate standby mode to
allow a quicker recovery into a fully active state. In Line-by-Line operation, the green and blue
channel PGAs are automatically powered down.
All the internal registers maintain their previously programmed value in power down modes and the
control interface inputs remain active. Table 3 summarises the power down control bit functions.
EN
0
SELDPD
0
0
1
Device completely powers down.
1
Device completely powers up.
X
Blocks with respective SELDIS[3:0] bit high are disabled.
Table 3 Power Down Control
LINE-BY-LINE OPERATION
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8195 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8195
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 20 shows the signal path when operating in colour line-by-line mode.
VRLC/VBIAS
VSMP
MCLK
CL
RS VS TIMING CONTROL
R
8
OFFSET
MUX
OFFSET
DAC
G
B
14-
BIT
ADC
DATA
I/O
PORT
RINP
RLC
RLC
RLC
CDS
+
PGA
8
+
OP[13:0]
INPUT
MUX
R
I/P SIGNAL
POLARITY
ADJUST
PGA
MUX
G
GINP
BINP
B
SEN/STB
SCK/RNW
SDI/DNA
RLC/ACYC
NRESET
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
RLC
DAC
4
INTERFACE
Figure 20 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
See Figure 4 for detailed timing information. The multiplexers change on the first MCLK rising edge
after RLC/ACYC is taken high. A write to the auto-cycle reset register causes these multiplexers to
be reset; selecting the RINP pin and the RED offset/gain registers. Alternatively, all three
multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the
desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA
and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible.
PD Rev 4.1 July 2005
22
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
