WM8195
Production Data
PARALLEL INTERFACE: REGISTER WRITE
Figure 17 shows register write in parallel mode. The parallel interface uses bits OP[13:6] of the
output bus and the STB, DNA and RNW pins. Pin RNW must be low during a write operation. The
DNA pin defines whether the data byte is address (low) or data (high). The 6-bit address (a5, 0, a3,
a2, a1, a0) is input into OP[11:6], LSB into OP[6], (OP[12] and OP[13] are ignored) when DNA is low,
then the 8-bit data word is input into OP[13:6], LSB into OP[6], when DNA is high. The data bus
OP[13:6] for both address and data is clocked in on the falling edge of STB. Note all valid registers
have address bit a4 equal to 0.
STB
Driven Externally
Driven by AFE
Driven by AFE
Hi-Z
Hi-Z
Normal Output Data
Normal Output Data
Address
Data
OP[13:6]
DNA
RNW
Figure 17 Parallel Interface Register Write
Using the parallel interface, a software reset is carried out by writing “000100” to OP[13:8] when
RNW and DNA are low. Any value of data can be written for this address when DNA changes to high
(i.e. Data = XXXXXXXX on OP[15:8]).
PARALLEL INTERFACE: REGISTER READ-BACK
Figure 18 shows register read-back in parallel mode. Read-back is initiated by writing the 6-bit
address (a5, 1, a3, a2, a1, a0) into OP[11:6] by pulsing the STB pin low. Note that a4 = 1 and pins
RNW and DNA are low. When RNW and DNA are high and STB is strobed again, the contents (d7,
d6, d5, d4, d3, d2, d1, d0) of the corresponding register (a5, 0, a3, a2, a1, a0) will be output on
OP[13:6], LSB on pin OP[6]. Until STB is pulsed low, the current contents of the ADC (shown as
Normal Output Data) will be present on OP[13:6]. Note that the register data becomes available on
the output data pins so OEB should be held low when read-back data is expected.
STB
Driven by AFE
Driven by AFE
Driven Externally
Address
Hi-Z
Hi-Z
Normal Output Data
Normal Output Data
OP[13:6]
DNA
Read Data
RNW
Figure 18 Parallel Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 24MHz and a per-pixel synchronisation clock
(VSMP) of up to 12MHz are required. These clocks drive a timing control block, which produces
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 5.
PD Rev 4.1 July 2005
20
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
