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WM8195_05 参数 Datasheet PDF下载

WM8195_05图片预览
型号: WM8195_05
PDF下载: 下载PDF文件 查看货源
内容描述: 14位12MSPS CIS / CCD模拟前端/数字转换器 [14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser]
分类和应用: 转换器
文件页数/大小: 33 页 / 374 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8195  
CONTROL INTERFACE  
The internal control registers are programmable via the serial or parallel digital control interface. The  
register contents can be read back via the parallel interface on pins OP[13:6], or via the serial  
interface on pin OP[13]/SDO.  
Note: It is recommended that a software reset is carried out after the power-up sequence, before  
writing to any other register. This ensures that all registers are set to their default values (as shown  
in Table 6).  
SERIAL INTERFACE: REGISTER WRITE  
Figure 15 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit  
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data  
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.  
When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the  
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.  
SCK  
a5  
0
a3  
a2  
a1  
a0  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
SDI  
Address  
Data Word  
SEN  
Figure 15 Serial Interface Register Write  
Using the serial interface, a software reset is carried out by writing to Address “000100” with any  
value of data (i.e. Data Word = XXXXXXXX).  
SERIAL INTERFACE: REGISTER READ-BACK  
Figure 16 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus  
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing  
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of  
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge  
of SCK). Note that pin SDO is shared with an output pin, OP[13], therefore OEB should always be  
held low when register read-back data is expected on this pin. The next word may be read in to SDI  
while the previous word is still being output on SDO.  
SCK  
a5  
1
a3 a2 a1 a0  
x
x
x
x
x
x
x
x
SDI  
Address  
Data Word  
SEN  
SDO/  
d7 d6 d5 d4 d3 d2 d1 d0  
OP[13]  
Output Data Word  
OEB  
Figure 16 Serial Interface Register Read-back  
PD Rev 4.1 July 2005  
19  
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