Production Data
WM8195
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals though
the WM8199. The values of V1 V2 and V3 are often calculated in reverse order during device
setup. The PGA value is written first to set tshe input Voltage range, the Offset DAC is then
adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is
set to position the reset level correctly during operation.
Note: Refer to WAN0123 for detailed information on device calibration procedures.
The following equations describe the processing of the video and reset level signals through
the WM8195.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (CDS operation) the previously sampled reset level, VRESET, is subtracted from the input
video.
V1
=
VIN - VRESET ................................................................... Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V1
=
VIN - VVRLC .................................................................... Eqn. 2
If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If RLCEXT = 0, VVRLC is the output from the internal RLC DAC.
VVRLC
=
(VRLCSTEP RLCV[3:0]) + VRLCBOT ................................. Eqn. 3
V
RLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the offset DAC output.
V2
=
V1 + {260mV (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
V3
=
V2 208/(283- PGA[7:0]) .............................................. Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 14-bit unsigned number, with input range configured by
PGAFS[1:0].
D1[13:0] = INT{ (V3 /VFS
D1[13:0] = INT{ (V3 /VFS
D1[13:0] = INT{ (V3 /VFS
)
)
)
16383} + 8191 PGAFS[1:0] = 00 or 01 ...... Eqn. 6
16383} PGAFS[1:0] = 11 ............... Eqn. 7
16383} + 16383 PGAFS[1:0] = 10 ............... Eqn. 8
where the ADC full-scale range, VFS = 3V.
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
D2[13:0] = D1[13:0]
(INVOP = 0) ...................... Eqn. 9
(INVOP = 1) ...................... Eqn. 10
D2[13:0] = 16383 – D1[13:0]
PD Rev 4.1 July 2005
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
