W90N745CD/W90N745CDG
Arbitration Control Register (ARBCON)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
ARBCON
Arbitration Control Register
0xFFF0_0004
R/W
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
25
17
9
24
16
8
RESERVED
20
19
RESERVED
12
11
RESERVED
4
3
2
1
0
RESERVED
IPACT
IPEN
PRTMOD
BITS
DESCRIPTION
[31:3]
RESERVED
-
Interrupt priority active.
When IPEN=”1”, this bit will be set when the ARM core has an
unmasked interrupt request. This bit is available only when the
PRTMOD=0.
[2]
IPACT
Interrupt priority enable bit
0 = the ARM core has the lowest priority.
1 = enable to raise the ARM core priority to second
This bit is available only when the PRTMOD=0.
Priority mode select
0 = Fixed Priority Mode (default)
1 = Rotate Priority Mode
[1]
[0]
IPEN
PRTMOD
Publication Release Date: September 22, 2006
- 43 -
Revision A2
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