W90N745CD/W90N745CDG
IDLE MODE
If the IDLE bit in Power Management Control Register (PMCON) is set, the ARM CORE clock source
will be halted, the ARM CORE will not go forward. The AHB or APB clocks still active except the clock
to cache controller and ARM are stopped. W90N745 will exit idle state when nIRQ or nFIQ from any
peripheral is revived; like keypad, timer overflow interrupts and so on. The memory controller can also
be forced to enter idle state if both MIDLE and IDLE bits are set. Software must switch SDRAM into
self-refresh mode before forcing memory to enter idle mode.
IDLE Period
FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
HCLK
(memc)
Case1. IDLE=1, PD=0, MIDLE=0
Figure 6.2.7 Clock management for system idle mode
IDLE Period
FOUT
(PLL)
HCLK
idle_state
MCLK
(ARM)
HCLK
(cache)
HCLK
(memc)
Case2. IDLE=1, PD=0, MIDLE=1
Figure 6.2.8 Clock management for system and memory idle mode
Publication Release Date: September 22, 2006
- 39 -
Revision A2
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