W90N745CD/W90N745CDG
EXTAL
USBCKS
FIN
GP0
1
0
USB
Module
Input Divider
(NR)
48MHz
Gen
PLL
INDV[4:0]
FBDV[8:0]
Output
Divider
(NO)
480MHz
FOUT
Charge
Pump
PFD
VCO
Internal
System
Clock
0
Clock
Divider
&
1
Feedback
Divider
(NF)
Selector
ECLKS
OTDV[1:0]
CLKS[2:0]
Figure 6.2.10 System PLL block diagram
The formula of output clock of PLL is:
NF
1
FOUT = FIN ∗
∗
NR NO
FOUT：Output clock of Output Divider
FIN：External clock into the Input Divider
NR：Input divider value (NR = INDV + 2)
NF：Feedback divider value (NF = FBDV + 2)
NO：Output divider value (NO = OTDV)
Publication Release Date: September 22, 2006
Revision A2
- 45 -
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