W90N745CD/W90N745CDG
PLL Control Register0 （PLLCON0）
W90N745 provides two clock generation options – crystal and oscillator. The external clock via
EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the
PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock
for the internal system clock, D15 pin must be pull-up.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
PLLCON
PLL Control Register
0xFFF0_0008
R/W
0x0000_2F01
31
23
15
30
29
21
13
5
28
27
19
11
3
26
18
10
25
17
9
24
RESERVED
22
14
6
20
RESERVED
12
16
PWDEN
8
FBDV
7
4
2
1
0
FBDV
OTDV
INDV
BITS
DESCRIPTION
[31:17]
RESERVED
PWDEN
-
Power down mode enable
[16]
0 = PLL is in normal mode (default)
1 = PLL is in power down mode
PLL VCO output clock feedback divider
[15:7]
FBDV
OTDV
INDV
Feedback Divider divides the output clock from VCO of PLL.
PLL output clock divider
OTDV [6:5]
DIVIDED BY
0
0
1
0
1
1
2
2
4
[6:5]
[4:0]
0
1
1
PLL input clock divider
Input divider divides the input reference clock into the PLL.
- 44 -
WINBOND [ WINBOND ]
