W90N745CD/W90N745CDG
6.2.7 Power-On Setting
After power on reset, there are eight Power-On setting pins to configure W90N745 system configuration.
POWER-ON SETTING PIN
Internal System Clock Select
Little/Big Endian Mode Select
D15
D14
Boot ROM/FLASH Data Bus Width
Default: Pull-Down in Normal Operation
Default: Pull-Up in Normal Operation
D [13:12]
D9
D8
D15 pin：Internal System Clock Select
If pin D15 is pull-down, the external clock from EXTAL pin is served as internal system clock.
If pin D15 is pull-up, the PLL output clock is used as internal system clock.
D14 pin：Little/Big Endian Mode Select
If pin D14 is pull-down, the external memory format is Big Endian mode.
If pin D14 is pull-up, the external memory format is Little Endian mode.
D [13:12] ： Boot ROM/FLASH Data Bus Width
D [13:12]
BUS WIDTH
8-bit
Pull-down
Pull-down
Pull-up
Pull-down
Pull-up
16-bit
Pull-down
Pull-up
RESERVED
RESERVED
Pull-up
6.2.8 System Manager Control Registers Map
REGISTER
PDID
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xX090_0745
0x0000_0000
0x0000_2F01
0x1FFF_3FX8
0x0001_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0xFFF0_0000
R
Product Identifier Register
ARBCON
PLLCON0
CLKSEL
0xFFF0_0004 R/W Arbitration Control Register
0xFFF0_0008 R/W PLL Control Register 0
0xFFF0_000C R/W Clock Select Register
0xFFF0_0010 R/W PLL Control Register 1
PLLCON1
I²SCKCON
0xFFF0_0014 R/W
Audio I²S Clock Control Register
IRQWAKECON 0xFFF0_0020 R/W IRQ Wakeup Control register
IRQWAKEFLAG 0xFFFF_0024 R/W IRQ wakeup Flag Register
PMCON
0xFFF0_0028 R/W Power Manager Control Register
0xFFF0_0030 R/W USB Transceiver Control Register
USBTxrCON
Publication Release Date: September 22, 2006
Revision A2
- 41 -
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