W90N745CD/W90N745CDG
I2C Command Register 0/1 (I2C_CMDR 0/1)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0x0000_0000
0x0000_0000
I2C_CMDR0 0xFFF8_6008 R/W I2C Command Register 0
I2C_CMDR1 0xFFF8_6108 R/W I2C Command Register 1
31
23
15
7
30
22
14
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
6
3
2
1
0
Reserved
START
STOP
READ
WRITE
ACK
NOTE: Software can write this register only when I2C_EN = 1.
BITS
DESCRIPTIONS
[31:5]
[4]
Reserved
START
Reserved
Generate Start Condition
Generate (repeated) start condition on I2C bus.
Generate Stop Condition
[3]
[2]
[1]
STOP
READ
WRITE
Generate stop condition on I2C bus.
Read Data From Slave
Retrieve data from slave.
Write Data To Slave
Transmit data to slave.
Send Acknowledge To Slave
When I2C behaves as a receiver, sent ACK (ACK = ‘0’) or NACK (ACK
= ‘1’) to slave.
[0]
ACK
NOTE: The START, STOP, READ and WRITE bits are cleared automatically while transfer finished. READ and WRITE cannot
be set concurrently.
Publication Release Date: September 22, 2006
- 345 -
Revision A2
WINBOND [ WINBOND ]
