W90N745CD/W90N745CDG
I2C Prescale Register 0/1 (I2C_DIVIDER 0 /1)
REGISTER
ADDRESS
R/W
R/W
R/W
DESCRIPTION
RESET VALUE
0x0000_0000
0x0000_0000
I2C_DIVIDER0 0xFFF8_6004
I2C_DIVIDER1 0xFFF8_6104
I2C Clock Prescale Register 0
I2C Clock Prescale Register 1
31
23
15
7
30
22
14
6
29
21
13
5
28
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
20
12
Reserved
DIVIDER[15:8]
4
3
1
0
DIVIDER[7:0]
BITS
DESCRIPTIONS
Clock Prescale Register
It is used to prescale the SCL clock line. Due to the structure of the I2C
interface, the core uses a 5*SCL clock internally. The prescale register must
be programmed to this 5*SCL frequency (minus 1). Change the value of the
prescale register only when the “I2C_EN” bit is cleared.
[15:0]
DIVIDER
Example: pclk = 32MHz, desired SCL = 100KHz
32 MHz
prescale
=
− 1 = 63 (dec ) = 3 F (hex )
5 ∗ 100 KHz
- 344 -
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