W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:12]
Reserved
Reserved
Received Acknowledge From Slave (Read only)
This flag represents acknowledge from the addressed slave.
0 = Acknowledge received (ACK).
I2C_RxAC
K
[11]
[10]
[9]
1 = Not acknowledge received (NACK).
I2C Bus Busy (Read only)
I2C_BUSY 0 = After STOP signal detected.
1 = After START signal detected.
Arbitration Lost (Read only)
This bit is set when the I2C core lost arbitration. Arbitration is lost when:
I2C_AL
I2C_TIP
A STOP signal is detected, but no requested.
The master drives SDA high, but SDA is low.
Transfer In Progress (Read only)
0 = Transfer complete.
1 = Transferring data.
[8]
NOTE: When a transfer is in progress, you will not allow writing to any
register of the I2C master core except SWR.
Transmit Byte Counts
These two bits represent how many bytes are remained to transmit. When a
byte has been transmitted, the Tx_NUM will decrease 1 until all bytes are
transmitted (Tx_NUM = 0x0) or NACK received from slave. Then the
interrupt signal will assert if IE was set.
[5:4]
Tx_NUM
0x0 = Only one byte is left for transmission.
0x1 = Two bytes are left to for transmission.
0x2 = Three bytes are left for transmission.
0x3 = Four bytes are left for transmission.
[3]
[2]
Reserved
IF
Reserved
Interrupt Flag
The Interrupt Flag is set when:
Transfer has been completed.
Transfer has not been completed, but slave responded NACK (in multi-byte
transmit mode).
Arbitration is lost.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Interrupt Enable
[1]
[0]
0 = Disable I2C Interrupt.
1 = Enable I2C Interrupt.
I2C Core Enable
IE
I2C_EN
0 = Disable I2C core, serial bus outputs are controlled by SDW/SCW.
1 = Enable I2C core, serial bus outputs are controlled by I2C core.
Publication Release Date: September 22, 2006
- 343 -
Revision A2
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