W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
Reserved
[5:3]
Reserved
PRIORITY
Priority Level
Every interrupt source must be assigned a priority level during
initiation. Among them, priority level 0 has the highest priority and
priority level 7 the lowest. Interrupt sources with priority level 0 are
promoted to FIQ. Interrupt sources with priority level other than 0
belong to IRQ. For interrupt sources of the same priority level that
located in the lower channel number has higher priority.
[2:0]
AIC Interrupt Raw Status Register (AIC_IRSR)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
R
0x0000_0000
AIC_IRSR 0xFFF8_2100
Interrupt Raw Status Register
31
IRS31
23
30
IRS30
22
29
28
IRS28
20
27
IRS27
19
26
IRS26
18
25
24
IRS29
21
IRS25
17
IRS24
16
IRS23
15
IRS22
14
IRS21
13
IRS20
12
IRS19
11
IRS18
10
IRS17
9
IRS16
8
IRS8
IRS15
7
IRS14
6
IRS13
5
IRS12
4
IRS11
3
IRS10
2
IRS9
1
0
IRS7
IRS6
IRS5
IRS4
IRS3
IRS2
IRS1
RESERVED
BITS
DESCRIPTIONS
This register records the intrinsic state within each interrupt channel.
IRSx: Interrupt Status
[31:1]
IRSx
Indicate the intrinsic status of the corresponding interrupt source
0 = Interrupt channel is in the voltage level 0
1 = Interrupt channel is in the voltage level 1
Reserved
[0]
Reserved
- 304 -
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