W90N745CD/W90N745CDG
Interrupt Masking
Each interrupt source, including FIQ, can be enabled or disabled individually by using the command
registers AIC_MECR and AIC_MDCR. The status of interrupt mask can be read in the read only
register AIC_IMR. A disabled interrupt doesn’t affect the servicing of other interrupts.
Interrupt Clearing and Setting
All interrupt sources (including FIQ) can be individually set or clear by respectively writing to the
registers AIC_SSCR and AIC_SCCR when they are programmed to be edge triggered. This feature of
the AIC is useful in auto-testing or software debugging.
Fake Interrupt
When the AIC asserts the nIRQ line, the processor enters interrupt mode and the interrupt handler
reads the AIC_IPER, it may happen that AIC de-asserts the nIRQ line after the processor has taken
into account the nIRQ assertion and before the read of the AIC_IPER.
This behavior is called a fake interrupt.
The AIC is able to detect these fake interrupts and returns all zero when AIC_IPER is read. The same
mechanism of fake interrupt occurs if the processor reads the AIC_IPER (application software or ICE)
when there is no interrupt pending. The current priority level is not updated in this situation. Hence, the
AIC_EOSCR shouldn’t be written.
ICE/Debug Mode
This mode allows reading of the AIC_IPER without performing the associated automatic operations.
This is necessary when working with a debug system. When an ICE or debug monitor reads the AIC
user interface, the AIC_IPER can be read. This has the following consequences in normal mode:
y
y
If there is no enabled pending interrupt, the fake vector will be returned.
If an enabled interrupt with a higher priority than the current one is pending, it will
be stacked.
In the second case, an End-of-Service command would be necessary to restore the state of the AIC.
This operation is generally not performed by the debug system. Therefore, the debug system would
become strongly intrusive, and could cause the application to enter an undesired state.
This can be avoided by using ICE/Debug Mode. When this mode is enabled. The AIC performs
interrupt stacking only when a write access is performed on the AIC_IPER. Hence, the interrupt
service routine must write to the AIC_IPER (any value) just after reading it. When AIC_IPER is written,
the new status of AIC, including the value of interrupt source number register (AIC_ISNR), is updated
with the value that is kept at previous reading of AIC_IPER The debug system must not write to the
AIC_IPER as this would cause undesirable effects.
The following table shows the main steps of an interrupt and the order in which they are performed
according to the mode:
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