W90N745CD/W90N745CDG
Sub-block reset control register (ACTL_RESET)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xFFF0_9004 R/W
Sub block reset control
0x0000_0000
ACTL_RESET
The value in ACTL_RESET register control the reset operation in each sub block.
31
23
15
30
22
14
29
21
13
28
20
12
27
19
11
26
25
17
9
24
16
18
ACTL_RESET
10
8
AC_RECOR
D
RECORD_SINGLE[1:0]
PLAY_SINGLE[1:0]
Reserved
2
7
6
5
4
3
1
0
AC_PLAY
Reserved
AC_RESET
I²S_RECORD
I²S_PLAY
I²S_RESET
BITS
DESCRIPTIONS
[31:17]
Reserved
-
Audio controller reset control bit
1 = the whole audio controller is reset
0 = the audio controller is normal operation
The ACTL_RESET bit is read/write
[16]
ACTL_RESET
record single/dual channel select bits
2’b11= the record is dual channel
2’b01= the record only select left channel
2’b10= the record only select right channel
2’b00 is reserved
RECORD_SINGLE
[1:0]
[15:14]
Note that, when ADC is selected as record path, it only
support left channel record.
The PLAY_SINGLE[1:0] bits are read/write
Publication Release Date: September 22, 2006
- 237 -
Revision A2
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