W90N745CD/W90N745CDG
31
23
30
22
29
21
28
20
12
27
19
11
26
18
10
25
17
9
24
16
15
Reserved
7
14
Reserved
6
13
Reserved
5
8
I²S_AC_PIN_SEL
0
R_DMA_IRQ T_DMA_IRQ
Reserved
3
2
1
4
Reserved
BLOCK_EN[1:0]
FIFO_TH
Reserved
Reserved
BITS
[15]
[14]
[13]
DESCRIPTIONS
Reserved
Reserved
Reserved
-
-
-
When recording, when the DMA destination current address reach the DMA
destination end address or middle address, the R_DMA_IRQ bit will be set to
1 automatically, and this bit could be cleared to 0 by CPU. The bit is
hardwired to ARM as interrupt request signal with an inverter.
[12]
[11]
R_DMA_IRQ
T_DMA_IRQ
The R_DMA_IRQ bit is read/write (write 1 to clear)
Transmit DMA interrupt request bit. When DMA current address reach the
middle address (((ACTL_DESE – ACTL_DESB)-1)/2 + ACTL_DESB) or
reach the end address ACTL_DESB, the bit T_DMA_IRQ will be set to 1, and
this bit could be clear to 0 by write “1” by CPU. And the bit is hardwired to
ARM as interrupt request signal with an inverter.
The T_DMA_IRQ bit is read/write (write 1 to clear).
I²S or AC-link pin selection
• If I²S_AC_PIN_SEL = 0, the pins select I²S
• If I²S_AC_PIN_SEL = 1, the pins select AC-link
The I²S_AC_PIN_SEL bis is read/write
[8]
I²S_AC_PIN_SEL
FIFO threshold control bit
• If FIFO_TH=0, the FIFO threshold is 8 level
• If FIFO_TH=1, the FIFO threshold is 4 level
The FIFO_TH bit is read/write
[7]
[6]
FIFO_TH
Reserved
Audio interface type selection
• If BLOCK_EN[0]=0/1, I²S interface is disable/enable
• If BLOCK_EN[1]=0/1, AC-link interface is disable/enable
The BLOCK_EN[1:0] bits are read/write
[2:1]
[0]
BLOCK_EN[1:0]
Reserved
- 236 -
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