W90N745CD/W90N745CDG
BITS
[31]
DESCRIPTIONS
RESERVED
TC_WIDTH
-
[30:28]
nRTC/nWTC active width selection, from 1 to 7 HCLK cycles.
External request pin selection, if GDMAMS [3:2]=00, REQ_SEL will
be don’t care.
If REQ_SEL [27:26]=00, external request don’t use.
If REQ_SEL [27:26]=01, use nXDREQ.
[27:26]
REQ_SEL
If REQ_SEL [27:26]=10, external request don’t use.
If REQ_SEL [27:26]=11, external request don’t use.
nXDREQ High/Low active selection
1’b0 = nXDREQ is LOW active.
1’b1 = nXDREQ is HIGH active.
[25]
[24]
[23]
REQ_ATV
ACK_ATV
RW_TC
nXDACK High/Low active selection
1’b0 = nXDACK is LOW active.
1’b1 = nXDACK is HIGH active.
Read/Write terminal count output selection.
1’b0 = output to nRTC.
1’b1 = output to nWTC.
Source address Boundary alignment Error flag
If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00
If TWS [13:12]=01, GDMA_SRCB [0] should be 0
[22]
SABNDERR The address boundary alignment should be depended on TWS [13:12].
1’b0 = the GDMA_SRCB is on the boundary alignment.
1’b1 = the GDMA_SRCB not on the boundary alignment
The SABNDERR register bits just can be read only.
Destination address Boundary alignment Error flag
If TWS [13:12]=10, GDMA_DSTB [1:0] should be 00
If TWS [13:12]=01, GDMA_DSTB [0] should be 0
[21]
[20]
DABNDERR The address boundary alignment should be depended on TWS [13:12].
1’b0 = the GDMA_DSTB is on the boundary alignment.
1’b1 = the GDMA_DSTB not on the boundary alignment
The DABNDERR register bits just can be read only.
GDMA Transfer Error
1’b0 = No error occurs
GDMATERR
1’b1 = Hardware sets this bit on a GDMA transfer failure
Transfer error will generate GDMA interrupt
- 160 -
WINBOND [ WINBOND ]
