W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:5]
Reserved
BistFail
-
The BIST Fail indicates if the BIST test fails or succeeds. If the
BistFail is low at the end, the embedded SRAM pass the BIST test,
otherwise, it is faulty. The BistFail will be high once the BIST
detects the error and remains high during the BIST operation. If
BistFail[2] high indicates the embedded SRAM for TxFIFO BIST
test failed. If BistFail[3] high indicates the embedded SRAM for
RxFIFO BIST test failed.
[3:2]
The BistFail is a write clear field. Write 1 to this field clears the
content and write 0 has no effect.
The BIST Operation Finish indicates the end of the BIST
operation. When BIST controller finishes all operations, this bit will
be high.
[1]
[0]
Finish
BMEn
The Finish is a write clear field. Write 1 to this field clears the
content and write 0 has no effect.
The BIST Mode Enable is used to enable the BIST operation. If
high enables the BIST controller to do embedded SRAM test. This
bit is also used to do the reset for BIST circuit. It is necessary to
reset the BIST circuit one clock cycle at least in order to initialize
the BIST properly.
The BMEn can be disabled by write 0.
Publication Release Date: September 22, 2006
- 157 -
Revision A2
WINBOND [ WINBOND ]
