W90N745CD/W90N745CDG
6.6 GDMA Controller
The W90N745 has a two-channel general DMA controller, called the GDMA. The two-channel GDMA
performs the following data transfers without the CPU intervention:
y
y
y
Memory-to-memory (memory to/from memory)
Memory –to – IO
IO- to -memory
The on-chip GDMA can be started by the software or external DMA request nXDREQ. Software can also
be used to restart the GDMA operation after it has been stopped. The CPU can recognize the completion
of a GDMA operation by software polling or when it receives an internal GDMA interrupt. The W90N745
GDMA controller can increment source or destination address, decrement them as well, and conduct 8-
bit (byte), 16-bit (half-word), or 32-bit (word) data transfers.
The GDMA includes the following features
y
y
y
y
AMBA AHB compliant
Supports 4-data burst mode to boost performance
Provides support for external GDMA device
Demand mode speeds up external GDMA operations
6.6.1 GDMA Functional Description
The GDMA directly transfers data between source and destination. The GDMA starts to transfer data
after it receives service requests from nXDREQ signal or software. When the entire data have been
transferred completely, the GDMA becomes idle. Nevertheless, if another transfer is needed, then the
GDMA must be programmed again. There are three transfer modes:
Single Mode
Single mode requires a GDMA request for each data transfer. A GDMA request (nXDREQ or
software) causes one byte, one half-word, or one word to transfer if the 4-data burst mode is
disabled, or four times of transfer width is the 4-data burst mode is enabled.
Block Mode
The assertion of a single GDMA request causes all of the data to be transferred in a single
operation. The GDMA transfer is completed when the current transfer count register reaches zero.
Demand Mode
The GDMA continues transferring data until the GDMA request input nXDREQ becomes inactive.
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