W90N745CD/W90N745CDG
Debug Mode MAC Information Register (DMMIR)
The DMMIR keeps the information of MAC module for debug.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
DMMIR
0xFFF0_3214
R
Debug Mode MAC Information Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
27
19
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
12 11
RBC
4
3
1
0
RBC
BITS
[31:16]
[15:0]
DESCRIPTIONS
Reserved
RBC
-
Receive Byte Count
BIST Mode Register (BISTR)
The BISTR controls the BIST (Built In Self Test) for embedded SRAM, 256B for RxFIFO and 256B for
TxFIFO.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
BISTR
0xFFF0_3300
R/W BIST Mode Register
0x0000_0000
31
23
15
7
30
22
14
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
Reserved
19
Reserved
11
Reserved
6
3
1
0
Reserved
BistFail
Finish
BMEn
- 156 -
WINBOND [ WINBOND ]
