W90N745CD/W90N745CDG
Channel 0/1 Destination Base Address Register (GDMA_DSTB0, DMA_DSTB1)
Channel 0/1 Destination Base Address Register (GDMA_DSTB0, GDMA_DSTB1)
The GDMA channel starts writing its data to the destination address as defined in this destination base
address register. During a block transfer, the GDMA determines successive destination addresses by
adding to or subtracting from the destination base address.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
Channel 0 Destination Base Address
Register
Channel 1 Destination Base Address
Register
GDMA_DSTB0 0xFFF0_4008
GDMA_DSTB1 0xFFF0_4028
R/W
0x0000_0000
R/W
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
DST_BASE_ADDR [31:24]
20 19
DST_BASE_ADDR [23:16]
12 11
DST_BASE_ADDR [15:8]
27
26
18
10
2
25
24
16
8
17
9
4
3
1
0
DST_BASE_ADDR [7:0]
BITS
DESCRIPTIONS
[31:0]
DST_BASE_ADDR
32-bit Destination Base Address
Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1)
REGISTER
ADDRESS
R/W
R/W
R/W
DESCRIPTION
RESET VALUE
0x0000_0000
0x0000_0000
GDMA_TCNT0
Channel 0 Transfer Count Register
0xFFF0_400C
0xFFF0_402C
GDMA_TCNT1
Channel 1 Transfer Count Register
31
23
15
7
30
29
21
13
5
28
27
19
11
3
26
18
10
2
25
24
16
8
Reserved
20
22
14
6
17
9
TFR_CNT [23:16]
12
TFR_CNT [15:8]
4
1
0
TFR_CNT [7:0]
- 164 -
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