W90N745CD/W90N745CDG
6.6.2 GDMA Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER ADDRESS R/W DESCRIPTION
Channel 0
GDMA_CTL0
GDMA_SRCB0 0xFFF0_4004 R/W
RESET VALUE
Channel 0 Control Register
0xFFF0_4000 R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Channel 0 Source Base Address Register
Channel 0 Destination Base Address Register
Channel 0 Transfer Count Register
GDMA_DSTB0
GDMA_TCNT0
0xFFF0_4008 R/W
0xFFF0_400C R/W
Channel 0 Current Source Address Register
GDMA_CSRC0 0xFFF0_4010
GDMA_CDST0 0xFFF0_4014
R
R
R
Channel 0 Current Destination Address
Register
0x0000_0000
0x0000_0000
Channel 0 Current Transfer Count Register
GDMA_CTCNT0 0xFFF0_4018
Channel 1
Channel 1 Control Register
GDMA_CTL1
0xFFF0_4020 R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Channel 1 Source Base Address Register
Channel 1 Destination Base Address Register
Channel 1 Transfer Count Register
GDMA_SRCB1 0xFFF0_4024 R/W
GDMA_DSTB1
GDMA_TCNT1
0xFFF0_4028 R/W
0xFFF0_402C R/W
Channel 1 Current Source Address Register
GDMA_CSRC1 0xFFF0_4030
GDMA_CDST1 0xFFF0_4034
GDMA_CTCNT1 0xFFF0_4038
R
R
R
Channel 1 Current Destination Address
Register
0x0000_0000
0x0000_0000
Channel 1 Current Transfer Count Register
Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1)
REGISTER
GDMA_CTL0
GDMA_CTL1
ADDRESS
0xFFF0_4000
0xFFF0_4020
R/W
R/W
R/W
DESCRIPTION
Channel 0 Control Register
Channel 1 Control Register
RESET VALUE
0x0000_0000
0x0000_0000
31
RESERVED
23
RW_TC
15
30
29
28
20
27
REQ_SEL
19 18
26
25
24
TC_WIDTH
REQ_ATV
ACK_ATV
22
21
17
BLOCK
9
BME
1
16
SOFTREQ
SABNDERR DABNDERR GDMAERR AUTOIEN
TC
10
14
RESERVED
6
13
12
11
8
SIEN
0
DM
TWS
SBMS RESERVED
7
5
4
3
2
SAFIX
DAFIX
SADIR
DADIR
GDMAMS
RESERVED GDMAEN
Publication Release Date: September 22, 2006
Revision A2
- 159 -
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