W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
Destination Address Direction
[4]
DADIR
1’b0 = Destination address is incremented successively
1’b1 = Destination address is decremented successively
GDMA Mode Select
00 = Software mode (memory-to-memory)
01 = External nXDREQ mode for external device
10 = Reserved
[3:2]
GDMAMS
11 = Reserved
[1]
[0]
Reserved
GDMAEN
-
GDMA Enable
1’b0 = Disables the GDMA operation
1’b1 = Enables the GDMA operation; this bit will be clear automatically
when the transfer is complete on AUTOIEN [19] register bit is on Disable
mode.
Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1)
The GDMA channel starts reading its data from the source address as defined in this source base
address register.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0x0000_0000
0x0000_0000
Channel 0 Source Base Address Register
Channel 1 Source Base Address Register
GDMA_SRCB0 0xFFF0_4004 R/W
GDMA_SRCB1 0xFFF0_4024 R/W
31
23
15
7
30
22
14
6
29
21
13
5
28
SRC_BASE_ADDR [31:24]
20 19
SRC_BASE_ADDR [23:16]
12 11
SRC_BASE_ADDR [15:8]
27
26
18
10
2
25
17
9
24
16
8
4
3
1
0
SRC_BASE_ADDR [7:0]
BITS
DESCRIPTIONS
[31:0]
SRC_BASE_ADDR 32-bit Source Base Address
Publication Release Date: September 22, 2006
Revision A2
- 163 -
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