W90N745CD/W90N745CDG
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
26
25
17
9
24
16
8
Reserved
18
Reserved
10
Enable
Out
Reserved
4
3
2
1
0
Config
BITS
DESCRIPTIONS
[31:24]
Reserved
Enable
-
The Function Enable outputs two function enable signals to
external stimulus circuit.
[23:22]
At this stage, only the bit 22 is used for external random collision
generator. The random collision generator used only in FPGA
emulation.
[21:8]
[7:6]
Reserved
Out
-
The Flag Out provides two output flags to trigger Logic Analyzer for
debug. These two bits can be written at any time.
The Configuration controls which group of internal signals can be
multiplexed out for debug. Each group includes 16 signals.
[5:0]
Config
CONFIG
SIGNALS
CONFIG
6’h01
SIGNALS
OUT [6], TransDone, GrantLost,
OUT [6], DMode_TxBuf_CS [6:0]
DMode_TXFSM_CS [7:0]
Trans_CTR [4:0], LAST,
TransCtrExpire,
6’h00
DMode_AHB_CS [5:0]
OUT [6], TXFIFO_HT, TXFIFO_LT,
DMode_TFF_CS [4:0],
OUT [6], DMode_RXBuf_CS [5:0],
DMode_RXFSM_CS [8:0]
6’h02
6’h04
6’h03
6’h05
DMode_RFF_CS [7:0]
WRITE, RFF_WPTR [5:0],
RXFIFO_HT,
TxBuf_DRDY, TFF_WPTR [5:0],
TX_START,
RXFIFO_LT, RxBuf_ACK, RFF_RPTR
[5:0]
TXSTART, READ, TFF_RPTR [5:0]
- 154 -
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