W90N745CD/W90N745CDG
Finite State Machine Register 1 (FSM1)
The FSM1 shows the current value of the FSM (Finite State Machine) of the function module in EMC.
The FSM1 is read only and write to it has no effect. The FSM1 is used only for debug.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
FSM1
0xFFF0_320C
R
Finite State Machine Register 1
0x1100_0100
31
Reserved
23
30
29
28
20
27
19
11
3
26
25
24
16
8
ARB_FSM
21
TxPause_FSM
22
14
6
18
17
9
Reserved
15
13
5
12
10
AHB_FSM
2
Reserved
7
4
1
0
Reserved
BITS
[31]
DESCRIPTIONS
Reserved
-
[30:28]
[27:24]
[23:14]
[13:8]
[7:0]
ARB_FSM
Internal Arbiter FSM
TxPause_FSM
Reserved
Transmit PAUSE Control Frame FSM
-
AHB_FSM
[13:8]: AHB Master FSM
RESERVED
-
Debug Configuration Register (DCR)
The DCR is for debug only to multiplex different signal group out. In FPGA emulation, the signals are
outputted to probe pins in emulation board. In real chip, the signals are outputted through the GPIO
pins.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
DCR
0xFFF0_3210 R/W Debug Configuration Register
0x0000_003f
Publication Release Date: September 22, 2006
Revision A2
- 153 -
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