WED9LC6816V
White Electronic Designs
SDRAM Current State Truth Table (cont.)
Command
Current State
Action
Notes
SDCE#
SDRAS #
SDCAS#
SDWE#
A12 & A13 (BA)
A11-A0
Description
Mode Register Set
Auto or Self Refresh
Precharge
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
ILLEGAL
ILLEGAL
X
X
X
L
H
H
L
X
Row Address
Column
Column
X
ILLEGAL
L
H
L
BA
BA
BA
X
Bank Activate
Write
ILLEGAL
H
H
H
H
ILLEGAL
Refreshing
L
H
L
Read
ILLEGAL
H
H
Burst Termination
No Operation
No Operation; Idle after tRC
No Operation; Idle after tRC
H
X
X
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
X
X
H
H
X
X
H
BA
Row Address
Bank Activate
Mode Register
Accessing
L
H
L
L
BA
Column
Write
ILLEGAL
L
L
L
H
H
H
L
H
H
H
L
BA
X
Column
Read
ILLEGAL
ILLEGAL
X
X
Burst Termination
No Operation
H
X
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current
State then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
