W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
FIGURE 5 – MODE REGISTER (MR) DEFINITION
MODE REGISTER (MR)
ꢀhe mode register is used to define the specific mode of
operation of the DDR2 SDRAM. ꢀhis definition includes
the selection of a burst length, burst type, CT, operating
mode, DTTRESEꢀ, write recovery, and power-down mode,
as shown in Figure 5. Contents of the mode register can be
altered by re-executing the TOAD MODE (TM) command.
If the user chooses to modify only a subset of the MR
variables, all variables (M0–M14) must be programmed
when the command is issued.
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
01 PD
MR
WR
DTT ꢀM CAS# Tatency Bꢀ Burst Tength
Mode
Normal
ꢀest
M7
0
M2 M1 M0
Burst Tength
Reserved
Reserved
4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
PD mode
M12
0
Fast Exit
(Normal)
Slow Exit
ꢀhe mode register is programmed via the TM command
(bits BA2–BA0 = 0, 0, 0) and other bits (M12–M0) will
retain the stored information until it is programmed again
or the device loses power (except for bit M8, which is
self-clearing). Reprogramming the mode register will
not alter the contents of the memory array, provided it is
performed correctly.
DTT Reset
No
M8
0
8
1
Reserved
Reserved
Reserved
Reserved
1
Yes
(Tow Power)
WRIꢀE RECOVERY
M11 M10 M9
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
Burst ꢀype
Sequential
Interleaved
M3
0
3
ꢀhe TM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts
are in progress. ꢀhe controller must wait the specified
4
1
5
6
CAS Tatency (CT)
M6 M5 M4
Reserved
Reserved
t
time MRD before initiating any subsequent operations
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
such as an ACꢀIVE command. Violating either of these
requirements will result in unspecified operation.
Reserved
Reserved
Mode Register Definition
Mode Register (MR)
M15 M14
3
0
1
0
1
0
0
1
1
4
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
BURST LENGTH
5
6
Burst length is defined by bits M0–M3, as shown in Figure
5. Read and write accesses to the DDR2 SDRAM are
burst-oriented, with the burst length being programmable
to either four or eight. ꢀhe burst length dete rmines
the maximum number of column locations that can be
accessed for a given READ or WRIꢀE command.
Reserved
Note: 1. Not used on this part
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved. ꢀhe burst type is selected
via bit M3, as shown in Figure 5. ꢀhe ordering of accesses
within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in ꢀable
2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst
mode only. For 8-bit burst mode, full interleave address
ordering is supported; however, sequential address
ordering is nibble-based.
When a READ or WRIꢀE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. ꢀhe block is uniquely selected by
A2–Ai when BT = 4 and by A3–Ai when BT = 8 (where
Ai is the most significant column address bit for a given
configuration). ꢀhe remaining (least significant) address
bit(s) is (are) used to select the starting location within the
block. ꢀhe programmed burst length applies to both READ
and WRIꢀE bursts.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
