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W3H64M72E-ESC 参数 Datasheet PDF下载

W3H64M72E-ESC图片预览
型号: W3H64M72E-ESC
PDF下载: 下载PDF文件 查看货源
内容描述: 64M X 72 DDR2 SDRAM 208 PBGA多芯片封装 [64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 30 页 / 942 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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W3H64M72E-XSBX  
White Electronic Designs  
ADVANCED*  
NOTES:  
ENABLE command provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits  
E7, E8 and E9 can be set to "0" or "1;" Micron recommends setting them to "0".  
10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is  
required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide  
LOW to BA2 = BA1 = BA0 = 0.) CKE must be HIGH the entire time. .  
11. Issue PRECHARGE ALL command.  
1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled.  
To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must  
be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs  
must be less than VCCQ during voltage ramp time to avoid DDR2 SDRAM device  
latch-up). At least one of the following two sets of conditions (A or B) must be  
met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF, and  
12. Issue two or more REFRESH commands.  
V
TT are between their minimum and maximum values as stated in DC Operating  
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e.,  
to program operating parameters without resetting the DLL). To access the mode  
registers, BA0 = 0, BA1 = 0, BA2 = 0.  
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits  
E7, E8, and E9 to “1,” and then setting all other desired parameters. To access the  
extended mode register, BA2 = 0, BA1 = 0, BA0 = 1.  
Conditions table):  
A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must  
take no longer than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V.  
Once supply voltage ramping is complete (when VCCQ crosses VCC (MIN), DC  
Operating Conditions table specifications apply.  
V
V
V
CC, VCCQ are driven from a single power converter output  
TT is limited to 0.95V MAX  
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7,  
E8, and E9 to “0,” and then setting all other desired parameters. To access the  
extended mode registers, BA2 = 0, BA1 = 0, BA0 = 1.  
16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock  
cycles after the DLL RESET at Tf0.  
REF tracks VCCQ/2; VREF must be within 0.3V with respect to VCCQ/2 during  
supply ramp time.  
CCQ ≥ VREF at all times  
V
B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage  
ramping, for both AC and DC levels, until supply voltage ramping completes  
(VCCQ crosses VCC [MIN]). Once supply voltage ramping is complete, DC  
Operating Conditions table specifications apply.  
• Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must  
be ≤ 200ms from when VCC ramps from 300mV to VCC (MIN)  
• Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time  
from when VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤  
500ms; while VCC is ramping, current can be supplied from VCC through the  
device to VCCQ  
VREF must track VCCQ/2, VREF must be within 0.3V with respect to VCCQ/2  
during supply ramp time; VCCQ ≥ VREF must be met at all times  
• Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to  
when VTT (MIN) is achieved must be no greater than 500ms  
2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during  
device power-up prior to VREF. being stable. After state T0, Cke is required to have  
SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for  
the duration on the initialization sequence.  
3. PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode  
Register, EMR = extended mode register, EMR2 = extended mode register 2,  
EMR3 = extended mode register 3, REF = REFRESH command, ACT = ACTIVE  
command, A10 = PRECHARGE ALL, CODE = desired value for mode registers  
(blank addresses are required to be decoded), VALID - any valid command/  
address, RA = row address, bank address.  
4. DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#,  
RDQS, RDQS#, DQ represents DQ0-71.  
5. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or  
DESELECT commands, then take CKE HIGH.  
6. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.  
7. Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command,  
provide LOW to BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or  
"1;" all others must be "0".  
8. Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command,  
provide HIGH to BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0".  
9. Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
March 2006  
Rev. 1  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com