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W3H64M72E-ESC 参数 Datasheet PDF下载

W3H64M72E-ESC图片预览
型号: W3H64M72E-ESC
PDF下载: 下载PDF文件 查看货源
内容描述: 64M X 72 DDR2 SDRAM 208 PBGA多芯片封装 [64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 30 页 / 942 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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W3H64M72E-XSBX  
White Electronic Designs  
ADVANCED*  
EXTENDED MODE REGISTER (EMR)  
ꢀhe extended mode register controls functions beyond  
those controlled by the mode register; these additional  
functions are DTT enable/disable, output drive strength,  
on die termination (ODꢀ) (Rꢀꢀ), postedAT, off-chip driver  
impedance calibration (OCD), DQS# enable/disable,  
RDQS/RDQS# enable/disable, and output disable/enable.  
ꢀhese functions are controlled via the bits shown in  
Figure 7. ꢀhe EMR is programmed via the TOAD MODE  
(TM) command and will retain the stored information  
until it is programmed again or the device loses power.  
Reprogramming the EMR will not alter the contents of the  
memory array, provided it is performed correctly.  
ꢀhe EMR must be loaded when all banks are idle and  
no bursts are in progress, and the controller must wait  
the specified time tMRD before initiating any subsequent  
operation. Violating either of these requirements could  
result in unspecified operation.  
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION  
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3  
A2 A1 A0  
Address Bus  
Extended Mode  
Register (Ex)  
16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
02 out  
OCD Program  
Posted CAS#  
ODS DLL  
MRS  
RTT  
RTT  
RDQS DQS#  
Outputs  
Enabled  
Disabled  
E0  
0
DLL Ena ble  
Enable (Normal)  
E12  
0
Rtt (nominal)  
RTT disabled  
75  
E6 E2  
1
1
0
0
1
1
0
1
0
1
Disable (Test/Debug)  
Output Drive Strength  
RDQ S Ena ble  
150 Ω  
E11  
0
E1  
0
No  
50Ω  
Full strength (18 target)  
1
Yes  
1
Reduced strength (40 target)  
E10  
0
DQ S# Ena ble  
Posted CA S# A dditive Laten cy (AL)  
E5 E4 E3  
Enable  
Disable  
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
3
E9 E8 E7  
OCD Operation  
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD not supported  
Reserved  
4
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
1
OCD default state  
Mo de Regi ster Set  
Mode register set (MRS)  
E16 E15 E14  
0
1
0
1
0
0
0
0
0
0
1
1
Extended mode register (EMRS)  
Extended mode register (EMRS2)  
Extended mode register (EMRS3)  
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,  
then must be set to "0" before initialization is finished, as detailed in the  
initialization procedure.  
2.. E13 (A13) is not used on this device.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
March 2006  
Rev. 1  
12  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
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