W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
DLL RESET
TABLE 2 – BURST DEFINITION
DTT RESEꢀ is defined by bit M8, as shown in Figure 5.
Programming bit M8 to “1” will activate the DTT RESEꢀ
function. Bit M8 is self-clearing, meaning it returns back
to a value of “0” after the DTT RESEꢀ function has been
issued.
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Burst
Starting Column
Address
Length
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Anytime the DTTRESEꢀ function is used, 200 clock cycles
must occur before a READ command can be issued to
allow time for the internal clock to be synchronized with
the external clock. Failing to wait for synchronization
4
0
1
1
0
1
1
t
t
A2
0
A1
0
A0
0
to occur may result in a violation of the AC or DQSCK
parameters.
0-1-2-3-4-5-6-7
1-2-3-0-5-6-7-4
2-3-0-1-6-7-4-5
3-0-1-2-7-4-5-6
4-5-6-7-0-1-2-3
5-6-7-4-1-2-3-0
6-7-4-5-2-3-0-1
7-4-5-6-3-0-1-2
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
WRITE RECOVERY
0
1
0
Write recovery (WR) time is defined by bits M9–M11, as
shown in Figure 5. ꢀhe WR register is used by the DDR2
SDRAM during WRIꢀE with auto precharge operation.
During WRIꢀE with auto precharge operation, the DDR2
SDRAM delays the internal auto precharge operation by
WR clocks (programmed in bits M9–M11) from the last
data burst.
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
WR values of 2, 3, 4, 5, or 6 clocks may be used for
programming bits M9–M11. ꢀhe user is required to
program the value of WR, which is calculated by dividing
tWR (in ns) by tCK (in ns) and rounding up a non integer
value to the next integer; WR [cycles] = tWR [ns] / tCK [ns].
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
POWER-DOWN MODE
Active power-down (PD) mode is defined by bit M12,
as shown in Figure 5. PD mode allows the user to
determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does
not apply to precharge PD mode.
OPERATING MODE
ꢀhe normal operating mode is selected by issuing a
command with bit M7 set to “0,” and all other bits set to
the desired values, as shown in Figure 5. When bit M7 is
“1,” no other bits of the mode register are programmed.
Programming bit M7 to “1” places the DDR2 SDRAM into a
test mode that is only used by the manufacturer and should
not be used. No operation or functionality is guaranteed
if M7 bit is ‘1.’
When bit M12 = 0, standard active PD mode or “fast-exit”
active PD mode is enabled. ꢀhe tXARD parameter is used
for fast-exit active PD exit timing. ꢀhe DTT is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode or “slow-
exit” active PD mode is enabled. ꢀhe tXARD parameter is
used for slow-exit active PD exit timing. ꢀhe DTT can be
enabled, but “frozen” during active PD mode since the exit-
to-READ command timing is relaxed. ꢀhe power difference
expected between PD normal and PD low-power mode is
defined in the ICC table.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
