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W3H64M72E-ESC 参数 Datasheet PDF下载

W3H64M72E-ESC图片预览
型号: W3H64M72E-ESC
PDF下载: 下载PDF文件 查看货源
内容描述: 64M X 72 DDR2 SDRAM 208 PBGA多芯片封装 [64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 30 页 / 942 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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W3H64M72E-XSBX  
White Electronic Designs  
ADVANCED*  
FIGURE 4 – POWER-UP AND INITIALIZATION  
Notes appear on page 9  
VCC  
V
CC  
Q
1
tVꢀD1  
V
ꢀꢀ  
V
REF  
k0  
l0  
m0  
g0  
h0  
i0  
j0  
e0  
f0  
ꢀc0  
d0  
b0  
ꢀ0  
a0  
t
CK  
CK#  
CK  
t
t
CT  
CT  
See  
note  
3
SSTL18  
TVCMOS  
TOW TEVET8  
8
CKE TOW TEVET  
ODꢀ  
COMMAND  
REF  
TM  
TM  
VATID3  
2
TM  
TM  
TM  
PRE  
PRE  
TM  
TM  
REF  
NOP  
DM7  
9
ADDRESS  
CODE  
CODE  
CODE  
A10 = 1  
CODE  
CODE  
CODE  
CODE  
A10 = 1  
VATID  
High-Z  
High-Z  
7
DQS  
DQ7  
High-Z  
Rꢀꢀ  
t
t
t
t
t
t
t
t
t
MRD  
ꢀ = 200µs (MIN)  
Power-up:  
CC and stable  
clock (CK, CK#)  
t
MRD  
t
ꢀ = 400ns  
(MIN)  
RPA  
MRD  
MRD  
MRD  
MRD  
EMR with  
DTT ENABTE5  
RPA  
RFC  
RFC  
MRD  
Seenote4  
V
EMR(2)  
EMR(3)  
MR w/o  
EMR with  
DTT RESEꢀ OCD Default  
EMR with  
10  
11  
OCD Exit  
Normal  
Operation  
3
200 cycles of CK  
MR with  
DTT RESEꢀ  
Indicates a break in  
time scale  
DON’ꢀ CARE  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
March 2006  
Rev. 1  
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com