W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
DESCRIPTION
ꢀhe 4Gb DDR2 SDRAM is a high-speed CMOS, dynamic
random-access memory containing 4,294,967,296 bits.
Each of the five chips in the MCP are internally configured
as 8-bank DRAM. ꢀhe block diagram of the device is
shown in Figure 2. Ball assignments and are shown in
Figure 3.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the
burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent
operation, thereby providing high, effective bandwidth by
hiding row precharge and activation time.
ꢀhe 4Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. ꢀhe
double data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two data
words per clock cycle at the I/O balls.Asingle read or write
access for the 4Gb DDR2 SDRAM effectively consists of
a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and four corresponding n-bit-wide,
one-half-clock-cycle data transfers at the I/O balls.
Aself refresh mode is provided, along with a power-saving
power-down mode.
All inputs are compatible with the JEDEC standard for
SSꢀTL18. All full drive-strength outputs are SSꢀTL18-
compatible.
GENERAL NOTES
•
ꢀhe functionality and the timing specifications
discussed in this data sheet are for the DTT-
enabled mode of operation.
A bidirectional data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during
WRIꢀEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRIꢀEs. ꢀhere are strobes,
one for the lower byte (TDQS, TDQS#) and one for the
upper byte (UDQS, UDQS#).
•
ꢀhroughout the data sheet, the various figures and
text refer to DQs as “DQ.” ꢀhe DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, each chip
is divided into 2 bytes, the lower byte and upper
byte. For the lower byte (DQ0–DQ7), DM refers to
TDM and DQS refers to TDQS. For the upper byte
(DQ8–DQ15), DM refers to UDM and DQS refers to
UDQS. Note that the there is no upper byte for U4
and therefore no UDM4.
ꢀhe 4Gb DDR2 SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going TOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
•
•
Complete functionality is described throughout
the document and any page or diagram may have
been simplified to convey a topic and may not be
inclusive of all requirements.
Read and write accesses to the DDR2 SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACꢀIVE command, which is then followed by a READ or
WRIꢀE command. ꢀhe address bits registered coincident
with the ACꢀIVE command are used to select the bank
and row to be accessed. ꢀhe address bits registered
coincident with the READ or WRIꢀE command are used
to select the bank and the starting column location for the
burst access.
Any specific requirement takes precedence over a
general statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
ꢀhe following sequence is required for power up and
initialization and is shown in Figure 4 on page 8.
ꢀhe DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with
another read, or a burst write of eight with another write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
