W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
TABLE – 1 BALL DESCRIPTIONS (continued)
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
A0-A12
Input
DQ0-71
I/O
I/O
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
UDQS, UDQS#
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
LDQS, LDQS#
I/O
VCC
VCCQ
VREF
VSS
Supply
Supply
Supply
Supply
-
Power Supply: 1.8V 0.1V
DQ Power supply: 1.8V 0.1V. Isolated on the device for improved noise immunity
SSTL_18 reference voltage.
Ground
NC
No connect: These balls should be left unconnected.
Future use; address bits A14 and A15 are reserved for future densities.
DNU
-
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
