W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
AC TIMING PARAMETERS (continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
533Mbs CL4
Symbol
400Mbs CL3
Unit
Parameter
DQ hold skew factor
Min
-
Max
400
Min
-
Max
450
tQHS
tAC
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
ps
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
DQS Low-Z window from CK/CK#
DQ Low-Z window from CK/CK#
-500
+500
-600
+600
tHZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ1
tAC(MN)
2*tAC(MN)
350
tAC(MN)
2*tAC(MN)
400
tLZ2
tDSa
tDHa
350
400
DQ and DM input setup time relative to DQS
tDSb
100
150
tDHb
225
275
DQ and DM input pulse width (for each input)
Data hold skew factor
tDIPW
tQHS
tQH
0.35
0.35
400
450
DQ-DQS hold, DQS to first DQ to go nonvalid, per access
Data valid output window (DVW)
tHP - tQHS
tQH - tDQSQ
0.35
tHP - tQHS
tQH - tDQSQ
0.35
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tDQSQ
tRPRE
tRPST
tWPRES
DQS input high pulse width
DQS input low pulse width
0.35
0.35
DQS output access time fromCK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
DQS-DQ skew, DOS to last DQ valid, per group, per access
DQS read preamble
-450
+450
-500
+500
0.2
0.2
0.2
0.2
300
1.1
0.6
350
1.1
0.6
0.9
0.4
0
0.9
0.4
0
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRE
0.25
0.25
tCK
DQS write postamble
tWPST
tDQSS
0.4
0.6
0.25
0.4
0.6
0.25
tCK
tCK
tCK
Positive DQS latching edge to associated clock edge
Write command to first DQS latching transition
-0.25
-0.25
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
26
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
