W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
AC TIMING PARAMETERS
-55°C ≤ TA < +125°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
533Mbs CL4
Symbol
400Mbs CL3
Unit
Parameter
Min
3,750
Max
8,000
8,000
0.52
Min
5,000
Max
8,000
8,000
0.52
CL=4
CL=3
tCK(4)
tCK(3)
tCH
ps
ps
tCK
tCK
ps
Clock cycle time
5,000
5,000
CK high-level width
CK low-level width
Half clock period
0.48
0.48
tCL
0.48
0.52
0.48
0.52
tHP
MIN (tCH, tCL)
tCKAVG
MIN (tCH, tCL)
tCKAVG
tCKAVG
tCKAVG
Absolute tCK
tCKabs
tCHabs
(MIN)+ tJITPER (MAX)+ tJITPER (MIN)+ tJITPER (MAX)+ tJITPER
ps
(MIN)
(MAX)
(MIN)
(MAX)
tCKAVG
tCKAVG
(MIN)* tCHAVG
(MIN)+ tJITDTY
(MIN)
tCKAVG
tCKAVG
(MAX)*
(MIN)* tCHAVG (MAX)* tCHAVG
(MIN)+ tJITDTY (MAX)+ tJITDTY
Absolute CK high-level width
tCHAVG
ps
(MAX)+ tJITDTY
(MAX)
(MIN)
(MAX)
tCKAVG
(MIN)*
tCLAVG
tCKAVG
(MAX)*
tCLAVG
tCKAVG
(MIN)*
tCLAVG
tCKAVG
(MAX)*
tCLAVG
Absolute CK low-level width
tCLabs
ps
(MIN)+ tJITDTY (MAX)+ tJITDTY (MIN)+ tJITDTY (MAX)+ tJITDTY
(MIN)
-125
-125
(MAX)
125
(MIN)
-125
-125
(MAX)
125
Clock jitter - period
tJITPER
tJITDUTY
tJITCC
tERR2per
tERR3per
tERR4per
tERR5per
tERR6-10per
tERR11-50per
ps
ps
ps
ps
ps
ps
ps
ps
ps
Clock jitter - half period
125
125
Clock jitter - cycle to cycle
250
250
Cumulative jitter error, 2 cycles
Cumulative jitter error, 3 cycles
Cumulative jitter error, 4 cycles
Cumulative jitter error, 5 cycles
Cumulative jitter error, 6-10 cycles
Cumulative jitter error, 11-50 cycles
-175
-225
-250
-250
-350
-450
175
225
250
250
350
450
-175
-225
-250
-250
-350
-450
175
225
250
250
350
450
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
25
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
