W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = 1.8V 0.1V; -55°C ≤ TA ≤ 125°C
Symbol Proposed Conditions
Operating one bank active-precharge current;
533 CL4 400 CL3
Units
ICC0
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
675
550
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDAD6W
ICC1
650
600
mA
Precharge power-down current;
ICC2P
ICC2Q
ICC2N
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
35
35
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
325
350
225
250
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
200
50
150
50
mA
mA
ICC3P
Active standby current;
ICC3N
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
375
300
900
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP
= tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
ICC4W
1,000
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4R
1,300
1,250
mA
tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
Burst auto refresh current;
ICC5
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,350
35
1,250
35
mA
mA
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
ICC6
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC
=
ICC7
t
RC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
1,750
1,650
mA
bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for
detailed timing conditions
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
24
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
