W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
PRECHARGE COMMAND
ꢀhe PRECHARGE command, illustrated in Figure 13, is
used to deactivate the open row in a particular bank or
the open row in all banks. ꢀhe bank(s) will be available
for a subsequent row activation a specified time (tRP)
after the PRECHARGE command is issued, except in
the case of concurrent auto precharge, where a READ or
WRIꢀE command to a different bank is allowed as long
as it does not interrupt the data transfer in the current
bank and does not violate any other timing parameters.
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRIꢀE
commands being issued to that bank. A PRECHARGE
command is allowed if there is no open row in that bank
(idle state) or if the previously open row is already in the
process of precharging. However, the precharge period
will be determined by the last PRECHARGE command
issued to the bank.
FIGURE 13 – PRECHARGE COMMAND
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
PRECHARGE OPERATION
ADDRESS
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA2–BA0 select the bank. Otherwise
BA2–BA0 are treated as “Don’t Care.”
ATT BANKS
A10
ONE BANK
BA0 - BA2
BA
When all banks are to be precharged, inputs BA2–BA0
are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRIꢀE commands being issued to that
bank. tRPA timing applies when the PRECHARGE (ATT)
command is issued, regardless of the number of banks
already open or closed. If a single-bank PRECHARGE
command is issued, tRP timing applies. tRPA(MIN) applies
to all 8-bank DDR2 devices.
DON’ꢀ CARE
Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").
cycles must then occur before a READ command can be
issued). ꢀhe differential clock should remain stable and
meet CKE specifications at least 1 x CK after entering
self refresh mode. All command and address input signals
except CKE are “Don’t Care” during self refresh.
t
t
SELF REFRESH COMMAND
ꢀhe procedure for exiting self refresh requires a sequence
of commands. First, the differential clock must be stable
and meet tCK specifications at least 1 x tCK prior to CKE
going back HIGH. Once CKE is HIGH (tCTE(MIN) has
been satisfied with four clock registrations), the DDR2
SDRAM must have NOP or DESETECꢀ commands issued
for tXSNR because time is required for the completion of
any internal refresh in progress. A simple algorithm for
meeting both refresh and DTT requirements is to apply
NOP or DESETECꢀ commands for 200 clock cycles before
applying any other command.
ꢀhe SETF REFRESH command can be used to retain
data in the DDR2 SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR2 SDRAM retains data without external clocking. All
power supply inputs (including VREF) must be maintained
at valid levels upon entry/exit and during SETF REFRESH
operation.
ꢀhe SETF REFRESH command is initiated like a
REFRESH command except CKE is TOW. ꢀhe DTT is
automatically disabled upon entering self refresh and is
automatically enabled upon exiting self refresh (200 clock
Note: Self refresh not available at military temperature..
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
21
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
