W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AT) is supported to make
the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3–E5 define the value
of AT, as shown in Figure 7. Bits E3–E5 allow the user
to program the DDR2 SDRAM with an inverse AT of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions
may result.
In this operation, the DDR2 SDRAM allows a READ or
t
WRIꢀE command to be issued prior to RCD (MIN) with
the requirement thatAT ≤ tRCD (MIN).Atypical application
using this feature would setAT = tRCD (MIN) - 1x tCK. ꢀhe
READ or WRIꢀE command is held for the time of the AT
before it is issued internally to the DDR2 SDRAM device.
RT is controlled by the sum of AT and CT; RT = AT+CT.
Write latency (WT) is equal to RT minus one clock; WT =
AT + CT - 1 x tCK.
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0
Address Bus
Exten ded Mo de
Register (Ex)
16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
01
01 01
01
01 01 01 01 01 01 01 01
01 01
EMR2
Mode Register Definition
M1 6 M15 M14
High Temperature Self Refresh rate enable
E7
0
Mode register (MR)
0
1
0
1
0
0
0
0
0
0
1
1
Commercial temperature default
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Industrial temperature option;
use if T C exceeds 85° C
1
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
