SCA8X0/21X0/3100 Series
SPI frame format and transfer protocol is presented in Figure 3.
Figure 3: SPI frame format
•
MOSI
•
•
•
•
A5:A0
RB/W
aPAR
DI7:DI0
Register address
Read/Write selection, '0'=read
Odd parity for bits A5:A0, RB/W
Input data for data write
•
MISO
•
•
•
Bit 1
FRME
Bit 3-5 status bits
not defined bit
Frame error indication (previous frame)
•
•
•
PORST Power On Reset Status
ST
SAT
Self Test error, not defined in SCA8X0
Output SATuration indicator, not defined in SCA8X0
always ‘0’, fixed bit
always ‘1’, fixed bit
Odd parity for output data (DO7:DO0)
Output data
•
•
•
•
Bit 6
Bit 7
dPAR
DO7:DO0
Each communication frame contains 16 bits. Please see Figure 3 for SPI bit definition. The first 8
bits in MOSI line contains info about the operation (read/write) and the register address being
accessed. First 6 bits define 6 bit address for selected operation, which is defined by bit 7 (‘0’ =
read ‘1’ = write), which is followed by odd parity bit (aPAR) for 8 bit pattern. The later 8 bits in MOSI
line contain data for a write operation and are ignored in case of read operation.
The first bits in MISO line are frame error bit (FRME, bit2) of previous frame, reset status bit
(PORST, bit3), self-test status bit (ST, bit4), saturation status (SAT, bit5), fixed zero bit (bit6), fixed
one bit (bit7) and odd parity bit of output data (dPAR, bit8)). Parity is calculated from data, which is
currently sent. The later 8 bits contain data for a read operation. During the write operation, these
data bits are previous data bits of addressed register.
For write commands, data is written into the addressed register on the rising edge of CSB. If the
command frame is invalid, data will not be written into the register.
The output register is shifted out MSB first over MISO output. Attempt to read a reserved register
outputs data of 00h.
When CSB is high state between data transfers, MISO line is in high-impedance state. If bit
CTRL.SDODIS is set to ‘1’, MISO line is always in high-impedance state. In multi-chip SPI bus
master can send data to all slave chips simultaneously.
4.1 Output of Acceleration Data
16-bit data is sent in 8-bit data bytes during two frames. Each frame contains odd parity bit of data
bits. Number format of acceleration data is two’s complement number.
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