SCA8X0/21X0/3100 Series
4.1.3 MOSI data of SPI commands
Table 8: MOSI data during SPI read command
Register to
Function
MOSI (15:0) [bits]
MOSI [hex]
be read
REVID
CTRL
STATUS
X_LSB
X_MSB
Read ASIC revision ID
Read CTRL register
Read Status register
Read acceleration on X-axis, LSB
Read acceleration on X-axis,
MSB
000000 01 xxxxxxxx
000001 00 xxxxxxxx
000010 00 xxxxxxxx
000100 00 xxxxxxxx
000101 01 xxxxxxxx
01xx
04xx
08xx
10xx
15xx
Y_LSB
Y_MSB
Read acceleration on Y-axis, LSB
Read acceleration on Y-axis,
MSB
000110 01 xxxxxxxx
000111 00 xxxxxxxx
19xx
1Cxx
Z_LSB
Z_MSB
Read acceleration on Z-axis, LSB
Read acceleration on Z-axis,
MSB
001000 00 xxxxxxxx
001001 01 xxxxxxxx
20xx
25xx
TEMP_LSB
TEMP_MSB
INT_STATUS Read INT_STATUS register
ID Read product ID number
Read temperature, LSB
Read temperature, MSB
010010 01 xxxxxxxx
010011 00 xxxxxxxx
010110 00 xxxxxxxx
100111 01 xxxxxxxx
49xx
4Cxx
58xx
9Dxx
Table 9: MOSI data during write command
Register to
be written
RESET
RESET
RESET
Function
MOSI (15:0) [bits]
MOSI [hex]
Reset component (data C'hex )
Reset component (data 5'hex )
Reset component (data F'hex )
000011 10 00001100
000011 10 00000101
000011 10 00001111
0E0C
0E05
0E0F
CTRL
CTRL
CTRL
CTRL
Set PORST to zero
Set chip to power down mode
Start self-diagnostic
000001 11 00000000
000001 11 00100000
000001 11 00001000
000001 11 00000100
0700
0720
0708
0704
Start memory self-test
4.2 Error Conditioning
4.2.1 FRME-bit
While sending a frame, if CSB is raised to 1 before sending 16 SCKs, the frame is considered
invalid. In SCA8X0 the frame error is raised if number of SCK pulses is not 16. In SCA21X0/3100
the frame error is raised only if number of SCK pulses is not divisible by 8 to support decremented
mode reading. When an invalid frame is received, the last command is simply ignored and the
register contents are left unchanged. Status bit STATUS.FRME is set to indicate this error
condition. During next SPI frame error bit send out as bit number 2. Bit STATUS.FRME will be
reseted, if correct frame is received.
4.2.2 PORST-bit
PORST length is 1bit in SPI frame. PORST bit is set if chip is reseted (HW reset by POR or supply
on/off) or under-voltage is detected. PORST bit is also set after power-up because chip has been in
reset state. PORST can be set to zero (reseted) by writing CTRL.PORST =0. Software (SW) reset
does not set PORST.
When CTRL.PORST bit is written to 0 via SPI, there is 300ns delay before register value is set to
zero.
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