SCA8X0/21X0/3100 Series
3.2 Operation control registers
3.2.1 Control Register (CTRL)
Address: 1h
Bits
Mode
Initial
Value
0
Name
Description
Reserved
7
6
RW
RW
0
PORST
1 means reset state. Bit gets set to 1 when the
digital gets reset by supply off control or under
voltage control. Bit is set after supply off/on
transition or startup. This bit can not be set by SPI
but it can be reset to 0 by writing a 0 over the SPI.
This bit is also sent as Bit3 of SPI output data frame
on MISO.
5
4
RW
RW
0
0
PDOW
SLEEP
Set chip to power down mode
Set chip to sleep mode. This bit can not be set to 1
if PDOW is already 1 or if PDOW is being set by the
current SPI command. (bit is not used in SCA8X0)
Set chip to self-test mode.
3
RW
0
ST
SCA8X0:
This bit starts mass deflection self-test (see also
ST_CFG bit). This bit is set to 0, when test is
passed. This bit can not be set to 1 if PDOW is
already 1 or if PDOW is being set by the current
SPI command. Test is done automatically during
start-up and acceleration output data can be read
during test.
SCA21X0 and SCA31X0:
Start continuous self-test calculation (STC). This bit
can not be set to 1 if PDOW or SLEEP or MTST is
already 1 or if PDOW or SLEEP or MTST is being
set by the current SPI command. Use
INT_STATUS.STC and ST bit of SPI frame for test
result monitoring.
2
RW
0
MST
Memory self-test function is activated, when user
sets bit to ‘1’. This bit is reset to 0 when test is over.
During memory self test, SPI access is prevented
for 85us. This bit can not be set to 1 if PDOW or
SLEEP is already 1 or if PDOW or SLEEP is being
set by the current SPI command. Test is done
automatically during start-up. Set other bits to zero
in CTRL register by previous SPI command before
starting memory self-test by CTRL.MST command.
Use STATUS.CSMERR for test result monitoring
and in SCA21X0/SCA31X0 ST bit in SPI frame.
Self-test configuration.
1
RW
0
ST_CFG
SCA8X0:
Select direction of mass deflection.
SCA21X0 and SCA31X0:
Start gravitation based start-up self-test calculation
(STS).
This bit can not be set to 1 if PDOW or SLEEP or
MTST is already 1 or if PDOW or SLEEP or MTST
is being set by the current SPI command. STC and
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