SCA8X0/21X0/3100 Series
Tempdec − 512LSB
Temp
[
°C
]
=
(
23 ±10 °C +
)
,
LSB
k
°C
where Temp[°C] is temperature in Celsius and Tempdec is temperature from TEMP_MSB and
TEMP_LSB registers in decimal format, bits(t9:0). k is temperature slope factor specified as
Min
2.8
Typ
3.2
Max
3.6
Unit
k
LSB/oC
3.1.6 Status Register (STATUS)
Address: 2h
Bits
Mode
Initial
Value
-
0
Name
Description
Reserved
Analog test mode status
1 – Test mode is active
7:3
2
-
R
ATEST
CSMERR
FRME
0 – Test mode is not active
1
0
R
R
0
0
EEPROM Checksum Error. In
SCA21X0/SCA31X0 ST bit of SPI frame is also
set if CSMERR is set.
SPI frame error. Bit is reset, when next correct
SPI frame is received. Bit is also visible in SPI
frame.
3.1.7 Interrupt Status Register (INT_STATUS)
Address: 16h
Bits
Mode
Initial
Value
0
Name
SAT
Description
7
6
R
R
Reserved
0
Saturation status of output data
1 – Over range detected, one or 2-3 of xyz axis is
saturated and output data is not valid.
0 – Data in range
SAT bit is also visible in SPI frame. This bit can be
active after start-up or reset stage before signal
path settles to final value and it has to be
acknowledged in start-up sequence (see Table 3)
or after SW reset or after PORST stage.
Status of gravitation based start-up self test
1 – Failure
5
R
R
R
0
STS
STC
0 – No failure
STS sets also ST bit in SPI frame.
Status of continuous self test
1 – Failure
0 – No failure
STC sets also ST bit in SPI frame.
Reserved
4
0
3:0
0000
The bits in this interrupt status register and corresponding SPI frame bits are cleared after register
has been read. Register reading is treated as interrupt acknowledgement signal. These bits are
kept active even failure condition is over if they are not acknowledged.
This register is not defined in SCA8X0.
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