SCA8X0/21X0/3100 Series
4.2.6 dPAR-bit
dPAR bit is odd parity bit of 8bit data that is currently sent in the frame. Master checks this bit and
compares to received data. Using dPAR at least one bit errors in data transmission can be
detected.
4.2.7 Fixed bits
Bits 6 and 7 are always fixed in MISO line. Bit 6 should always be '0' and bit 7 always '1'
4.2.8 Output data
1. Reset stage: When component is in reset or under voltage state, PORST bit in SPI frame and
CTRL.PORST bit is set. Furthermore, all register values are set to 00'hex.
2. Saturation: When acceleration exceeds measurement range, the output data is saturated to
specified positive or negative full-scale.
3. Self-diagnostic failure: In SCA21X0 and 31X0 the ST bit in SPI frame is set when memory
diagnostic or signal path diagnostic functions fail. Furthermore acceleration output data is
forced to 7FFF'hex if memory diagnostic fails or to FFFF'hex if signal path diagnostic functions
(STC/STS) fail.
VTI Technologies Oy
www.vti.fi
25/35
Doc. Nr. 82 694 00 C
VTI [ VTI TECHNOLOGIES ]
