SCA8X0/21X0/3100 Series
4.2.3 ST-bit (SCA21X0 / 3100)
Self-test frame status (ST) is set if STC or STS is alarmed or checksum is not passed.
•
CASE 1: Checksum fails and ST-frame bit is set 1. ST is set back to zero when (and only
if) new checksum calculation is passed.
•
CASE 2: ST-frame bit is set because STC or STS is alarmed. In this case ST-frame bit can
be cleared by INT_STATUS register reading.
ST bit is not defined in SCA8X0 series.
4.2.4 SAT-bit (SCA21X0 / 3100)
Saturation status (SAT) is set if any of axis xyz is saturated and it can be cleared by INT_STATUS
register reading. This bit is kept active even failure condition is over if it is not acknowledged.
Saturation limit varies between different product types. For example:
•
•
•
SCA2100 2 g product: x and y channel saturates to 2.27 g and SAT bit in SPI frame and in
INT_STATUS register is set, if 2.27 g is exceeded. Additional to this, if acceleration to z-
direction exceeds 4.54 g, SAT bit in SPI frame and in INT_STATUS register is set. In all
cases INT_STATUS register reading is needed for acknowledgement and acceleration
output data of any channel is not valid, when bit is active.
SCA2110 2 g product: x and z channel saturates to 2.27 g and SAT bit in SPI frame and in
INT_STATUS register is set, if 2.27 g is exceeded. Additional to this, if acceleration to y-
direction exceeds 4.54 g, SAT bit in SPI frame and in INT_STATUS register is set. In all
cases INT_STATUS register reading is needed for acknowledgement and acceleration
output data of any channel is not valid, when bit is active.
SCA2120 2 g product: y and z channel saturates to 2.27 g and SAT bit in SPI frame and in
INT_STATUS register is set, if 2.27 g is exceeded. Additional to this, if acceleration to x-
direction exceeds 4.54 g, SAT bit in SPI frame and in INT_STATUS register is set. In all
cases INT_STATUS register reading is needed for acknowledgement and acceleration
output data of any channel is not valid, when bit is active.
SAT bit is not defined in SCA8X0 series, but output saturates to the calibrated level. For example
acceleration output data of SCA8x0 2 g products saturates to 2.27 g.
4.2.5 aPAR-bit (SCA21X0 / 3100)
aPAR is odd parity bit of input address+RB/W-bit. Master write it and slave check that bit.
•
If there is parity error and RB/W='1', write command is ignored and frame error bit is set to
STATUS-register and to SPI frame. Next correct SPI frame will zero this bit.
•
If there is parity error and RB/W='0', read command is performed normally and frame error
bit is set to STATUS-register and to SPI frame. Next correct SPI frame will zero this bit.
aPAR bit is not checked in SCA8X0 series.
Table 10: Address parity
Address
Notes
A5
0
1
1
0
A4
0
1
0
1
A3
0
1
1
0
A2
0
1
0
1
A1
0
1
1
0
A0
0
1
0
1
RB/W
aPAR
0
1
1
0
1
0
1
0
correct frame
correct frame
correct frame
correct frame
VTI Technologies Oy
www.vti.fi
24/35
Doc. Nr. 82 694 00 C
VTI [ VTI TECHNOLOGIES ]
