Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 8. Power Down Mode and Clock Mask
(Burst Length = 4, CAS Burst Length = 4, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
t
t
CK2
IS
PDE
Valid
CS
RAS
CAS
WE
DSF
BS
A9
RAx
RAx
CAx
A0 ~ A8
DQM
DQ
tHZ
Hi-Z
Ax2
Ax0
Ax1
Ax3
PRECHARGE
STANDBY
ACTIVE
STANDBY
Read
Precharge
Command
Bank A
Clock Mask
Start
Power Down
Mode Exit
Clock Mask
End
Activate
Command
Bank A
Command
Bank A
Any
Command
Power Down
Mode Exit
Power Down
Mode Entry
Power Down
Mode Entry
Document:
Rev.1
Page12