Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 9.1 Random Column Read (Page within same Bank)
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK1
CS
RAS
CAS
WE
DSF
BS
RAz
A9
RAw
A0 ~ A8
RAw
RAz
CAw
CAz
CAx
CAy
DQM
DQ
Hi-Z
Aw0
Az2 Az3
Az0 Az1
Aw2
Ay3
Aw1
Ay2
Aw3
Ax0 Ax1 Ay0
Read
Ay1
Read
Read
Precharge
Command
Bank A
Activate
Command
Bank A
Command
Bank A
Command
Bank A
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Document:
Rev.1
Page13