VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
Electrical Characteristics and Recommended A.C. Operating Conditions
(V = 3.3V±0.3V, Ta = 0~70°C) (Note: 6, 7, 8, 9, 10) *** CL is CAS Latency.
DD
symbol
A.C. Parameter
-5
-6
-7
unit
Min. Max. Min. Max. Min. Max.
t
t
t
Row cycle time
45
15
15
54
18
18
62
20
20
RC
RAS to CAS delay
RCD
RP
ns
Precharge to refresh/row activate com-
mand
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Row activate to row activate delay
Row activate to precharge time
Write recovery time
10
12
14
RRD
RAS
WR
CK1
CK2
CK3
CH
30 100,000 36 100,000 40 100,000
1
14
7
1
16
8
1
18
9
CLK
CL* = 1
Clock cycle time
5
6
7
Clock high time
Clock low time
CL* = 1
1.5
1.5
2
2.5
2.5
2
CL
ns
11
5
13
5
15
6
AC1
AC2
AC3
T
Access time from CLK
(positive edge)
CL* = 2
CL* = 3
Transition time of CLK (Rise and Fall)
CAS to CAS Delay time
Data output hold time
4.5
10
5
5.5
10
0.5
1
0.5
10
0.5
1
1
CLK
ns
CCD
OH
2
2.5
2.5
2
Data output low impedance
2
2
LZ
CL = 1
3
5
5
5
3
5
5
5
3
6
6
5
HZ1
HZ2
HZ3
IS
Data output high impedance
CL = 2
3
3
3
CL = 3
Data/Address/Control Input setup time
Data/Address/Control Input hold time
Minimum CKE ”High”for Self-Refresh exit
Power Down Exit set-up time
3
3
3
1
1
1.5
1
1
1
IH
1
1
1
CLK
ns
SRX
PDE
RSC
BWC
DAL2
3
4
2
5
(Special) Mode Register Set Cycle time
Block Write Cycle time
2
2
CLK
CLK
1
1
1
1clk
1clk+
1clk
(CL = 2)
Data-in to ACT Command
+t
t
+t
RP
RP
RP
t
1clk
+t
1clk+
1clk
+t
(CL = 3)
DAL3
t
RP
RP
RP
t
t
Block Write to Precharge command
Refresh time
1
1
1
CLK
ms
BPL
32
32
32
REF
Document:1G5-0145
Rev.1
Page23
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
