VG4616321B/VG4616322B
262,144x32x2-Bit
Preliminary
CMOS Synchronous Graphic RAM
VIS
T6
T2
T7
T8
T1
T3
T4
T5
T0
CLK
Burst Stop
NOP
NOP
NOP
READ A
NOP
NOP
COMMAND
NOP
NOP
The burst ends after a delay equal to the CAS latency.
CAS Iatency = 1
DOUT A
DOUT A
DOUT A
3
DOUT A
1
0
2
t
,DQ’s
CK1
CAS Iatency = 2
,DQ’s
t
DOUT A
DOUT A
CK2
DOUT A
2
DOUT A
1
0
3
CAS Iatency = 3
,DQ’s
t
DOUT A
1
DOUT A
DOUT A
3
DOUT A
CK3
0
2
Termination of a Burst Write Operation (Burst Length > 4, CAS Latency = 1, 2, 3)
T6
T2
T7
T8
T1
T3
T4
T5
T0
CLK
NOP
NOP
NOP
NOP
Burst Stop
don’t care
NOP
NOP
WRITE A
DIN A0
NOP
COMMAND
CAS latency = 1, 2, 3
DQ’s
DIN A1
DIN A2
Input data for the Write is masked.
Termination of a Burst Write Operation (Burst Length = X, CAS Latency = 1, 2, 3)
15 Device Deselect command
(CS = ”H”)
The Device Deselect command disables the command decoder so that the RAS, CAS, WE
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is sim-
ilar to the No Operation command.
16 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS = ”L”, CAS = ”L”, WE = ”H”, DSF = ”L”, CKE = ”H”, BS, A0-A9 = Don’t care)
The AutoRefresh command is used during normal operation of the SGRAM and is anala-
gous to CAS-before-RAS(CBR) Refresh in conventional DRAMs. This command is non-persis-
tent, so it must be issued each time a refresh is required. The addressing is generated by the
internal refresh controller. This makes the address bits a “don’t care” during an AutoRefresh
command. The internal refresh counter increments automatically on every auto refresh cycle to
all of the rows. The refresh operation must be performed 2048 times within 32ms. The time
required to complete the auto refresh operation is specified by tRP(min.). To provide the AutoRe-
fresh command, both banks need to be in the idle state and the device is not in power down
mode (CKE is high in the previous cycle). This command must be followed by NOPs until the
auto refresh operations is completed. The precharge time requirement, tRP(min.). must be met
befor successive auto refresh operations are performed.
17 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS = ”L”, CAS = ”L”, WE = ”H”, DSF = ”L”, CKE = ”L”, BS, A0-A9 = Don’t care)
The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered,
all the inputs to the SGRAM becomes “don’t care” with the exception of CKE, which must remain
LOW. The refresh addressing and timing is internally generated to reduce power comsumption.
The SGRAM may remain in SelfRefresh mode for an indefinite period. Once the SGRAM enters
the SelfRefresh mode , tRAS(min.) is required before exit from SelfRefresh mode. The SelfRe-
fresh mode is exited by restarting the external clock and then asserting high on CKE(SelfRefresh
Exit command).
Document:1G5-0145
Rev.1
Page19
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
